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Basic timers (TIM6&TIM7)
RM0008
Figure 152. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
31
FF
32 33 34 35 36 00 01 02 03 04 05 06 07
36
Write a new value in TIMx_ARR
Figure 153. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload shadow register
F0
F5
F5
F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07
36
36
Write a new value in TIMx_ARR
15.3.3
380/995
Clock source
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 154 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Doc ID 13902 Rev 9
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